Systems and methods herein generally relate to performing a timing analysis of an integrated circuit design.
Delay calculations of circuit designs are used to ensure that the longest (critical) delay path does not exceed a required time maximum to process signals, and this is the process of checking the timing performance of the circuit. Delays of individual devices (e.g., a logic gate and the wires attached to it) are included in standard cell libraries, and the process of performing static timing analysis computes the delays of entire paths, by combining the previously computed delay of individual devices. However, sometimes devices perform differently based on their placement relative to other devices, and this can render the timing analysis of a circuit incorrect.